Analog-to-digital converters (ADCs) form an integral part of many electronic devices comprising digital signal processors (DSPs) in which an analog input signal is (down)converted into a digital signal for further processing. Examples of such electronic devices include video processing devices, mobile telecommunication devices, and so on.
Many of such devices require high-speed conversion of the analog input signal, as for instance is the case for streaming video processing. A well-known example of a high speed ADC is the flash ADC, which is schematically depicted in FIG. 1. The N-bit flash ADC in FIG. 1 has an analog input 100 that is fed to the respective inputs of 2N−1 comparators 120 that further receive a reference voltage on their other input generated by a resistive divider or ladder 110 connected between an upper reference voltage 112 and a lower reference voltage 114. The comparators 120 are typically clocked to sample the analog input at given points in time, i.e. at the edges of the clock signal. This is also known as the sampling rate of the ADC.
The reference voltage for each comparator is one least significant bit (LSB) greater than the reference voltage for the comparator immediately below ft. Each comparator produces a “1” when its analog input voltage is higher than the applied reference voltage. Otherwise, the comparator output is “0”. Thus, if the analog input is between reference voltages v4 and v5, comparators 120(1) up to and including 120(4) produce “1”s and the remaining comparators produce “0”s.
The point where the code changes from ones to zeros is the point where the input signal becomes smaller than the respective comparator reference voltage levels. This is known as thermometer code encoding. The thermometer code is decoded into the appropriate digital bit pattern 150 by a decoder 140.
The comparators 120 may form a cascade of wideband low gain stages. These stages are low gain because at high sampling frequencies it is difficult to achieve both wide bandwidth as well as high gain. The comparators 120 are designed for low voltage offset, such that the input offset of each comparator is much smaller than a least significant bit (LSB) of the flash ADC. This reduces the risk that the offset could falsely trip the comparator 120, resulting in a digital output code not representative of a thermometer code. A regenerative latch 130 may be used to store the clocked comparator results.
However, the ongoing miniaturization of electronic circuits such as DSPs makes it increasingly difficult to implement a flash ADC in modern IC technologies, due to the relatively large area required for the flash ADC. For instance, the flash ADC uses an area intensive reference ladder 110 to generate accurate reference voltages, and requires 2N−1 comparators to implement an N-bit ADC, which practically limits the ADC to an upper limit of 8 bits.
In addition, the offset of the comparators 120 has to be reduced due to the reducing supply voltages in new sub-micron-technologies, causing a reduction of the magnitude of the LSB voltage. The offset shifts the decision level of the comparator 120, which gives the flash ADC a non-linear amplitude quantizing transfer function. In the particular case where two consecutive comparators have an inverted offset greater than 0.5 LSB, the flash ADC loses its monotonicity.
The offset of the comparators 120 can be reduced in two ways. Firstly, the area of the input pair may be increased. Increasing the area of the input pairs of the comparators 120 increases their matching and reduces the spread on the comparator decision level. However, the area increase is undesirable. Moreover, this area increase reduces the speed of the comparators 120, which therefore is contradictory to the high-speed requirements of the flash ADC.
Alternatively, offset calibration techniques may be used. This however comes at the expense of a significant increase of the design complexity of the flash ADC, which increases the design time and risk, and thus cost of the ADC.